TSUOpen-source chip blueprint. License the RTL.
An open, royalty-free ISA + Verilog RTL design package for AI agent inference hardware. Download the blueprints, adapt to your process, tape out your own chips. RISC-V based. Community governed.
Four reference designs.
Pick a blueprint. Adapt to your foundry.
Each tier is a complete, synthesizable Verilog design package. License the RTL, integrate into your process, and manufacture at your chosen foundry. No royalties. No vendor lock-in.
| NPU Core | 16 TOPS · 8× RISC-V · 32GB LPDDR5 · 5W · $5K license |
| Fusion APU | 32 TOPS · 12× RISC-V + 256 GPU · 64GB LPDDR5X · 25W · $15K license |
| Enterprise Blade | 64 TOPS · 16× RISC-V + 512 GPU · 128GB LPDDR5X · 45W · $50K license |
| Foundry Edition | Custom · Scalable core count · Any foundry node · Flexible · Custom quote |
Unified memory fabric.
Zero copy. Coherent. Purpose-built.
All three compute domains — CPU, NPU, GPU — share a single, coherent memory space.
npu.matmul rd, rs1, rs2
npu.attn rd, rs1, rs2
npu.softmax rd, rs1
npu.rmsnorm rd, rs1, rs2
agt.enclave rd, rs1
agt.sign rd, rs1
agt.mesh.send rd, rs1, rs2
pwr.dvfs rd, rs1
Foundry Edition.
Custom node. Maximum performance.
For semiconductor foundries and enterprise partners requiring bleeding-edge fabrication. The Foundry Edition adapts the TSU architecture to custom process nodes (7nm, 5nm, 3nm) with denser logic, higher clock rates, and advanced packaging.
License the TSU-ISA and RTL for integration into your own process. Full design kit, verification suite, and engineering support included.
Purpose-built features.
No retrofitting.
Persistent KV-cache
4MB dedicated SRAM. Battery-backed DRAM. Cryptographic sealing per agent identity.
Secure enclave
Dedicated RV32IMC core. 64KB tamper-resistant SRAM. Hardware AES-256/GCM.
Multi-agent mesh
256 nodes via native 1GbE. Sub-10µs inter-node latency.
Deterministic scheduler
256 priority levels. WCET analysis. Deadline miss detection.
RV64GCBV + custom.
Sixteen first-class instructions.
Every custom instruction is a pipeline citizen — compiler-driven, deterministic, binary compatible across all three tiers.
npu.matmul rd, rs1, rs2
npu.attn rd, rs1, rs2
npu.softmax rd, rs1
npu.silu rd, rs1
npu.rmsnorm rd, rs1, rs2
npu.sparse rd, rs1, rs2
// Agent - security & mesh
agt.enclave rd, rs1
agt.sign rd, rs1
agt.verify rd, rs1, rs2
agt.kvcache.store rd, rs1
agt.kvcache.load rd, rs1
agt.mesh.send rd, rs1, rs2
agt.mesh.recv rd, rs1
// Power - dynamic control
pwr.domain rd
pwr.set rd, rs1
pwr.dvfs rd, rs1
Community-governed.
No company. No investors.
TSU is a protocol — not a startup. All funds go to the DAO treasury.
Help us tape out.
TSU Protocol is pre-tapeout and seeking $50K-$200K for our first MPW shuttle run (28nm or 22nm). DAO-governed, transparent, community-voted.